Application of Dynamic Pass-Transistor Logic to an 8-Bit Multiplier

Dynamic pass-transistor logic (PTL), which combines pass-transistor logic with dynamic logic, is proposed for high-performance VLSI circuit design. The dynamic PTL holds the merits of fast evaluation characteristics as dynamic logic. Moreover, because a pre-charged scheme solves the weak logic ‘high’ problem of a static PTL, an additional level restoration circuit is not needed. An 8-bit multiplier is designed using dynamic PTL for the evaluation of its characteristics. The multiplier consists of a Booth’s partial product generator and a [4 : 2] compressor for a partial product reduction tree. For the comparison of performance, the multiplier is also designed using conventional static CMOS logic. An HSPICE simulation is carried out with the 0.25 μm CMOS device model parameters used in Samsung Electronics Co. From the simulation, the delay of multiplier is 206.2 psec, and the power consumption is 117.5 mW with a 3.3 V supply voltage, a 1 GHz operation and a 60 C temperature. The results show that the multiplier designed by using dynamic PTL improves the speed by 2.5 times but consumes more power by 21 %; hence, the power delay product is improved by 50 % compared with a static CMOS.